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shanghai belling corp., ltd BL24C512 1 features two-wire serial interface, i 2 c tm compatible C bi-directional data transfer protocol wide-voltage operation C v cc = 1.7v to 5.5v speed: 400 khz (1.7v) and 1 mhz (2.5v~5.5v) standby current (max.): 1 m a, 1.7v operating current (max.): 2 ma, 1.7v hardware data protection C write protect pin sequential & random read features memory organization: 65,536 x 8 bits page size: 128 bytes page write mode C up to 128 bytes per page write self timed write cycle with auto clear: 5ms (max.) filtered inputs for noise suppression high-reliability C endurance: 1 million cycles C data retention: 100 years industrial temperature grades packages: soic/sop, tssop, dfn and csp lead-free, rohs, halogen free, green description the BL24C512 are eeprom devices that use the industrial standard 2-wire interface for communications. the BL24C512 contains a memory array of 512k-bits (65,536x8), which is organized in 128-byte per page . the eeprom can operate in a wide voltage range from 1.7v to 5.5v which fits most application. this produc t can provide a low-power 2-wire eeprom solution. the devic e is offered in lead-free, rohs, halogen free or green . the available package types are 8-pin soic/sop, tssop, dfn and csp. the BL24C512 is compatible with the industrial stand ard 2-wire bus protocol. if in case the bus is not resp onded, a new sent op-code command will reset the bus and the device will respond correctly. the simple bus consi sts of the serial clock wire (scl) and the serial data wire (sda). utilizing such bus protocol, a master device, such as a microcontroller, can usually control one or more sl ave devices, alike this BL24C512. the bit stream over th e sda line includes a series of bytes, which identifies a particular slave device, an instruction, an address within that slave device, and a series of data, if appropriate. the bl 24c512 also has a write protect pin (wp) to allow blocking any write operations over specified memory area. under no circumstance, the device will be hung up. in order to refrain the state machine entering into a wrong state during power-up sequence or a power toggle off-on condition, a power on reset circuit is embedded. du ring power-up, the device does not respond to any instru ctions until the supply voltage (v cc ) has reached an acceptable stable level above the reset threshold voltage. onc e v cc passes the power on reset threshold, the device is reset and enters into the standby mode. this would also a void any inadvertent write operations during power-up st age. during power-down process, the device will enter in to standby mode, once v cc drops below the power on reset threshold voltage. in addition, the device will be in standby mode after receiving the stop command, provided tha t no internal write operation is in progress. neverthele ss, it is illegal to send a command unless the v cc is within its operating level.
shanghai belling corp., ltd BL24C512 2 functional block diagram highvoltage generator timing& control eepromarray ydecoder xdecoder dataregister controllogic wordaddress counter slaveaddress register& comparator 5 6 7 1 2 3 4 8 gnd a2 a1 a0 wp scl sda vcc ack nmos di/o clock
shanghai belling corp., ltd BL24C512 3 pin configuration 8-pin soic/sop and tssop top view 8-lead dfn top view a0 a1 v cc scl sda gnd a2 wp 12 3 4 87 6 5 pin definition pin no. pin name i/o definition 1 a0 i device address input 2 a1 i device address input 3 a2 i device address input 4 gnd - ground 5 sda i/o serial address and data input and data out put 6 scl i serial clock input 7 wp i write protect input 8 v cc - power supply pin descriptions scl this input clock pin is used to synchronize the dat a transfer to and from the device. sda the sda is a bi-directional pin used to transfer add resses and data into and out of the device. the sda pin is an open drain output and can be wired with other open drain or open collector outputs. however, the sda pin requires a pull-up resistor connected to the power supply. a0, a1, a2 the a0, a1 and a2 are the device address inputs. typically, the a0, a1, and a2 pins are for hardware addressing and a total of 8 devices can be connecte d on a single bus system. when a0, a1, and a2 are left float ing, the inputs are defaulted to zero. wp wp is the write protect pin. while the wp pin is con nected to the power supply of BL24C512, the entire array be comes write protected (i.e. the device becomes read only). when wp is tied to ground or left floating, the normal w rite operations are allowed. v cc supply voltage gnd ground of supply voltage
shanghai belling corp., ltd BL24C512 4 device operation the BL24C512 serial interface supports communication s using industrial standard 2-wire bus protocol, such as i 2 c. 2-wire bus the two-wire bus is defined as serial data (sda), and serial clock (scl). the protocol defines any device t hat sends data onto the sda bus as a transmitter, and th e receiving devices as receivers. the bus is controll ed by master device that generates the scl, controls the b us access, and generates the start and stop conditions . the BL24C512 is the slave device. the bus protocol data transfer may be initiated only when the bus is not busy. during a data transfer, the sda line must remain st able whenever the scl line is high. any changes in the sda line while the scl line is high will be interpreted as a start or stop condition. the state of the sda line represents valid data afte r a start condition. the sda line must be stable for the durat ion of the high period of the clock signal. the data on th e sda line may be changed during the low period of the clock s ignal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated by a stop condition. start condition the start condition precedes all commands to the de vice and is defined as a high to low transition of sda wh en scl is high. the eeprom monitors the sda and scl lines and will not respond until the start condition is met. stop condition the stop condition is defined as a low to high tran sition of sda when scl is high. all operations must end with a stop condition. acknowledge after a successful data transfer, each receiving dev ice is required to generate an ack. the acknowledging device pulls down the sda line. reset the BL24C512 contains a reset function in case the 2 -wire bus transmission on is accidentally interrupted (e. g. a power loss), or needs to be terminated mid-stream. the re set is initiated when the master device creates a start co ndition. to do this, it may be necessary for the master devi ce to monitor the sda line while cycling the scl up to nine times. (for each clock signal transition to high, the mast er checks for a high level on sda.) standby mode while in standby mode, the power consumption is min imal. the BL24C512 enters into standby mode during one of the following conditions: a) after power-up, while no op -code is sent; b) after the completion of an operation and fo llowed by the stop signal, provided that the previous oper ation is not write related; or c) after the completion of any internal write operations. device addressing the master begins a transmission on by sending a st art condition, then sends the address of the particular slave devices to be communicated. the slave device address is 8 bits format as shown in figure. 1-5. the four most significant bits of the slave address are fixed (1010) for BL24C512. the next three bits, a0, a1 and a2, of the slave addr ess are specifically related to eeprom. up to eight BL24C512 units can be connected to the 2-wire bus. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bi t is set to 1, read operation is selected. while it is set to 0 , write operation is selected. after the master transmits the start condition and sl ave address byte appropriately, the associated 2-wire sl ave device, BL24C512, will respond with ack on the sda li ne. then BL24C512 will pull down the sda on the ninth clo ck cycle, signaling that it received the eight bits of data. the BL24C512 then prepares for a read or write opera tion by monitoring the bus. write operation byte write in the byte write mode, the master device sends the start condition and the slave address information (with th e r/w set to zero) to the slave device. after the slave gene rates an ack, the master sends the byte address that is to be written into the address pointer of the BL24C512. af ter receiving another ack from the slave, the master devic e transmits the data byte to be written into the addr ess
shanghai belling corp., ltd BL24C512 5 memory location. the BL24C512 acknowledges once more and the master generates the stop condition, at whi ch time the device begins its internal programming cycle. w hile this internal cycle is in progress, the device will not respond to any request from the master device. page write the BL24C512 is capable of 128-byte page-write opera tion. a page-write is initiated in the same manner as a byt e write, but instead of terminating the internal writ e cycle after the first data word is transferred, the maste r device can transmit up to 127 more bytes. after the receipt of each data word, the eeprom responds immediately with an ack on sda line, and the seven lower order data word address bits are internally incremented by one, whi le the higher order bits of the data word address remain c onstant. if a byte address is incremented from the last byte of a page, it returns to the first byte of that page. if the m aster device should transmit more than 128 bytes prior to issuin g the stop condition, the address counter will roll over , and the previously written data will be overwritten. once a ll 128 bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the BL24C512 in a single write cycle. all inputs are disabled until co mpletion of the internal write cycle. acknowledge (ack) polling the disabling of the inputs can be used to take adv antage of the typical write cycle time. once the stop cond ition is issued to indicate the end of the host's write oper ation, the BL24C512 initiates the internal write cycle. ack polli ng can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the eeprom is still busy with the write operation, no ack will be returned. if the BL24C512 ha s completed the write operation, an ack will be returne d and the host can then proceed with the next read or wri te operation. read operation read operations are initiated in the same manner as write operations, except that the (r/w) bit of the slave a ddress is set to 1. there are three read operation options: current address read, random address read and sequential re ad. current address read the BL24C512 contains an internal address counter wh ich maintains the address of the last byte accessed, incremented by one. for example, if the previous op eration is either a read or write operation addressed to th e address location n, the internal address counter wo uld increment to address location n+1. when the eeprom receives the slave addressing byte with a read operat ion (r/w bit set to 1), it will respond an ack and tran smit the 8-bit data byte stored at address location n+1. the master should not acknowledge the transfer but should gene rate a stop condition so the BL24C512 discontinues transmis sion. if 'n' is the last byte of the memory, the data fro m location '0' will be transmitted. (refer to figure 1-8. current address read diagram.) random address read selective read operations allow the master device to select at random any memory location for a read operation. the master device first performs a 'dummy' write operat ion by sending the start condition, slave address and byte address of the location it wishes to read. after the BL24C512 acknowledges the byte address, the master device resends the start condition and the slave add ress, this time with the r/w bit set to one. the eeprom then responds with its ack and sends the data requested. t he master device does not send an ack but will generate a stop condition. (refer to figure 1-9. random address read diagram.) sequential read sequential reads can be initiated as either a curren t address read or random address read. after the BL24C512 sends the initial byte sequence, the master device now responds with an ack indicating it require s additional data from the BL24C512. the eeprom continues to output data for each ack received. the m aster device terminates the sequential read operation by pulling sda high (no ack) indicating the last data word to be read, followed by a stop condition. the data output is se quential, with the data from address n followed by the data f rom address n+1,n+2 ... etc. the address counter increm ents by one automatically, allowing the entire memory conte nts to be serially read during sequential read operation. when the memory address boundary of the array is reached , the
shanghai belling corp., ltd BL24C512 6 address counter rolls over to address 0, and the device continues to output data. (refer to figure 1-10. seq uential read diagram). diagrams figure 1-1. typical system bus configuration figure 1-2. output acknowledge figure 1-3. start and stop conditions bl24cxxx
shanghai belling corp., ltd BL24C512 7 figure 1-4. data validity protocol figure 1-5. slave address figure 1-6. byte write figure 1-7. page write
shanghai belling corp., ltd BL24C512 8 figure 1-8. current address read figure 1-9. random address read figure 1-10. sequential read
shanghai belling corp., ltd BL24C512 9 timing diagrams figure 1-11. bus timing figure 1-12. write cycle timing sda wordn ack stop condition start condition t wr scl
shanghai belling corp., ltd BL24C512 10 electrical characteristics absolute maximum ratings symbol parameter value unit v s supply voltage -0.5 to + 6.5 v v p voltage on any pin C0.5 to v cc + 0.5 v t bias temperature under bias C55 to +125 c t stg storage temperature C65 to +150 c i out output current 5 ma note: stress greater than those listed under absolute max imum ratings may cause permanent damage to the devi ce. this is a stress rating only and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reliability. operating range range ambient temperature (t a ) v cc industrial C40c to +85c 1.7v to 5.5v note: industrial grade for commercial applications (0 c to +70 c). capacitance symbol parameter [1, 2] conditions max. unit c in input capacitance v in = 0v 6 pf c i/o input / output capacitance v i/o = 0v 8 pf notes: [1] tested initially and after any design or process c hanges that may affect these parameters and not 100 % tested. [2] test conditions: t a = 25c, f = 1 mhz, v cc = 5.0v.
shanghai belling corp., ltd BL24C512 11 dc electrical characteristic industrial: t a = C40c to +85c, v cc = 1.7v ~ 5.5v symbol parameter [1] v cc test conditions min. max. unit v cc supply voltage 1.7 5.5 v v ih input high voltage 0.7*v cc v cc +1 v v il input low voltage -1 0.3* v cc v i li input leakage current 5 v v in = v cc max -- 2 a i lo output leakage current 5v -- 2 a v ol1 output low voltage 1.7v i ol = 0.15 ma 0.2 v v ol2 output low voltage 3v i ol = 2.1 ma 0.4 v i sb1 standby current 1.7v v in = v cc or gnd 1 a i sb2 standby current 2.5v v in = v cc or gnd 2 a i sb3 standby current 5v v in = v cc or gnd 3 a i cc1 read current 1.7v read at 400 khz 0.5 ma 2.5v read at 1 mhz 1 ma 5.5v read at 1 mhz 1 ma i cc2 write current 1.7v write at 400 khz 2 ma 2.5v write at 1 mhz 3 ma 5.5v write at 1 mhz 3 ma note: the parameters are characterized but not 100% tested.
shanghai belling corp., ltd BL24C512 12 ac electrical characteristic industrial: t a = C40c to +85c, supply voltage = 1.7v to 5.5v symbol parameter [1] [2] 1.7v v cc <2.5v 2.5v v cc <4.5v 4.5v v cc 5.5v unit min. max. min. max. min. max. f scl sck clock frequency 400 1000 1000 khz t low clock low period 1200 400 400 ns t high clock high period 600 400 400 ns t r rise time (scl and sda) 300 300 300 ns t f fall time (scl and sda) 300 100 100 ns t su:sta start condition setup time 600 200 200 ns t su:sto stop condition setup time 600 200 200 ns t hd:sta start condition hold time 600 200 200 ns t su:dat data in setup time 100 40 40 ns t hd:dat data in hold time 0 0 0 ns t aa clock to output access time (scl low to sda data out valid) 100 900 50 400 50 400 ns t dh data out hold time (scl low to sda data out change) 100 50 50 ns t wr write cycle time 5 5 5 ms t buf bus free time before new transmission 1000 400 400 ns t su:wp wp pin setup time 600 400 400 ns t hd:wp wp pin hold time 1200 1200 1200 ns t noise suppression time 100 50 50 ns notes: [1] the parameters are characterized but not 100% test ed. [2] ac measurement conditions: r l (connects to v cc ): 1.3 k (2.5v, 5.0v), 10 k (1.7v) c l = 100 pf input pulse voltages: 0.3*v cc to 0.7*v cc input rise and fall times: 50 ns timing reference voltages: half v cc level
shanghai belling corp., ltd BL24C512 13 package information soic/sop 8l 150mil sop package outline min nom max min nom max a 1.35 -- 1.75 0.053 -- 0.069 a1 0.10 -- 0.25 0.004 -- 0.010 b 0.33 -- 0.51 0.013 -- 0.020 d 4.80 -- 5.00 0.189 -- 0.197 e 5.80 -- 6.20 0.228 -- 0.244 e1 3.80 -- 4.00 0.150 -- 0.157 e l 0.38 -- 1.27 0.015 0.050 l1 zd 0 -- 8 0 -- 8 0.545 ref. 0.050 bsc. 0.010 bsc. 0.021 ref. symbols dimensions in millimeters dimensions in inches 1.27 bsc. 0.25 bsc.
shanghai belling corp., ltd BL24C512 14 tssop 8l 3x4.4mm tssop package outline a2 a1 b min nom max min nom max a -- -- 1.20 -- -- 0.047 a1 0.05 -- 0.15 0.002 -- 0.006 a2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 -- 0.30 0.007 -- 0.012 c 0.09 -- 0.20 0.004 -- 0.008 d 2.90 3.00 3.10 0.114 0.118 0.122 e 4.30 4.40 4.50 0.169 0.173 0.177 e1 e l 0.45 0.60 0.75 0.018 0.024 0.030 0 -- 8 0 -- 8 0.252 bsc 0.026 bsc symbols dimensions in millimeters dimensions in inches 0.65 bsc 6.4 bsc a 12(4x) 0.10mm l c e e1 e d note: 1.controllingdimension:mm 2.dimensiondande1donotincludemoldprotrusion 3.dimensionbdoesnotincludedambarprotrusion/intr usion. 4.refertojedecstandardmo153aa 5.drawingisnottoscale 6.packagemayhaveexposedtiebar. 1 8
shanghai belling corp., ltd BL24C512 15 dfn 8l 3x3mm dfn package outline min nom max min nom max a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 -- 0.05 0.000 -- 0.002 b 0.17 0.22 0.27 0.007 0.009 0.011 d d2 2.375 2.385 2.395 0.094 0.094 0.094 e e2 1.635 1.645 1.655 0.064 0.065 0.065 e k 0.23 0.28 0.33 0.009 0.011 0.013 l 0.35 0.40 0.45 0.014 0.016 0.018 symbols dimensions in millimeters dimensions in inches 0.50bsc. 3.00 bsc 0.118 bsc 3.00 bsc 0.118 bsc 0.020bsc note: 1.controllingdimension:mm 2.drawingisnottoscale topview bottomview sideview d e pin#1dotby marking d2 e e2 k l b a a1 pin#1 identification chamfer

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